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Altera_Forum
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15 years ago

Clock frequency vs. Latency issues for an IIR filter

The LPM arithmetic & logic functions in Quartus have an option to specify the required Output Latency in terms of no. of clock cycles. An obvious choice is to set this value to the least i.e. '1' in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

if you register both the inputs and outputs, you have a 2 cycle latency. This will work for sure at 20MHz. Actually, I did a quick implementation of that equation on a Cyclone III, with all the factors being registers, and the fMax is 93MHz.

To achieve a single cycle latency, one has to drop either the input or output registers. And then one has to do a more careful analysis, including ADC tco or DAC tsu/th and board delays. But my guess is that yeah, it's probably doable at 20 MHz.

Quite honestly, I never use BDF, so I'm totally unfamiliar with it. But yes, it should be related to pipelining options or registered input/output options.