Honored Contributor
Honored Contributor@rbugalho: Wow ! Thanks for such a quick reply. But some doubts do lurk in my mind.
--- Quote Start --- Assuming you're working with 16 bit ( wide signals, you should be do do all that in a single 50ns cycle. --- Quote End --- Really !!! (Yes I am working with 16-bit data) You mean to say that my entire algorithm can get executed within a single 50 ns time-unit, and my input-to-output latency will be just 1 sampling period. This is really alluring, I need to try this out. --- Quote Start --- What you need is to disable the registers in the several LPM modules and register only the input signals from the ADC and the output signals to the DAC. --- Quote End --- I understand what you mean here, in terms of pure Verilog coding. But how do I do this in Quartus (since I am using LPM symbols in a Quartus BDF file) When I do the "Open Design File" option on each LPM module, it takes me to the corresponding Verilog code. but i already see no registers here, all inputs outputs & intermediate sub-wires - are (by default) of 'wire' data type. Do I check the "no" answer to "do you want to pipeline the function?" option inside every LPM module ?
