New ContributorClock Domains and Clock Domain Crossing (CDC)
The FPGA design uses two clock domains: 100 MHz and 40 MHz.
Clock domain crossing (CDC) between these domains is handled as follows:
- Data transfer (100 MHz → 40 MHz): A FIFO is used to provide reliable synchronization and maintain data integrity during transfers from the faster to the slower clock domain.
- Control signals (100 MHz ↔ 40 MHz): Shift-register synchronizers are used to safely transfer control signals in both directions between the two domains.
The CDC implementation follows the recommendations outlined in the Altera Clock Domain Crossing tutorial.
The main question concerns how timing constraints are applied:
1-Do the set_max_skew and set_data_delay constraints have any impact after defining the following asynchronous clock-group constraint?
set_clock_groups -asynchronous -group {clkA} -group {clkB}
2-Additionally, how should the multiplier values (e.g., 0.8 or 0.9) used in set_max_skew and set_data_delay be determined or selected?
Thanks.
The whole point here is to guide the Fitter after cutting timing between the two clock domains, so the answer to your first question is yes. The two domains are cut from each other and then set_max_skew and set_data_delay are used to define skew between bus paths between the clock domains and the data path delay between the endpoints of the two sides of the cut paths.
As for the values to use, just use the recommended values you show in that slide.
