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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

clock divider with counter

Hey guys, I am trying to design a counter . First of all, i have a clock divider block which will take on-board clock of 50 Mhz and will change it into frequency of 1Hz. The output frequency ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The port connections are still incorrect. You should follow mvanpelt's suggestion and use named ports during the instantiation. By being more explicit, it will show you some of your mistakes.

e.g.

This: 


up_counter ch_upc
(
  .clk         ( clk_out ),
  .enable      ( enable  ),
  .reset       ( reset   ),
  .out         ( out     )
);

vs. 


module up_counter(clk, enable, reset, out );
...
endmodule;
up_counter ch_upc(clk_out, reset, enable, out);