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WGith's avatar
WGith
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Clock Control IP Issue

Using the Clock Control IP in the Stratix 10 as a clock gating controller with one clock input. The clock enable is in Distributed Sector Level and Negative Latch mode.​

Quartus Prime Version 18.1.0 Build 09/21/2018 SJ Pro Edition.

If the design is limited in size, it does seem to be able to compile without issue. But once we run the full design, which takes up about 40% of a Stratix 10, then the crash occurs during the fitter stage. The pop-up box to send a report to Intel does come up, and I do send it to Intel.

Compile effort is Balanced, although I have seen the same issue with some of the Performance switches turned on.​

​

Commenting out the Clock Control IP and using the non gated clock, no issue with compiling is found.

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    What are the specs of the computer you're trying to compile on, especially how much RAM do you have?

    • WGith's avatar
      WGith
      Icon for Occasional Contributor rankOccasional Contributor
      7 years ago
      Problem Details Error: Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp, Line: 4539 TIMING CHECK FAILED: ATOM Type: NADDER_CLK_DIVIDER (atom id 1592918) with OTERM type O_CLOCK_DIV2 which feeds ITERM type CLK of ATOM Type : NADDER_FF (atom id 3251011) has multiple top-level ports and couldn't determine which one leads to ITERM Stack Trace: 0xc6cf6: PTI_TDB_BUILDER::report_multiple_top_level_ports_message + 0x136 (tsm_pti) 0x18623: PTI_TDB_BUILDER::get_output_node_for_ic_edge + 0x1e7 (tsm_pti) 0x18e81: PTI_TDB_BUILDER::build_or_update_tdb_netlist + 0x431 (tsm_pti) 0x5eb7e: PTI_DELAY_ANNOTATOR::annotate_routing_and_cell + 0x15fe (tsm_pti) 0x5f4d8: PTI_DELAY_ANNOTATOR::build_multicorner + 0x358 (tsm_pti) 0xad945: FITCC_TDC_UTILITY::initialize_dat + 0xb95 (FITTER_FITCC) 0xaeaca: FITCC_TDC_UTILITY::setup_tdc_utility + 0x1da (FITTER_FITCC) 0xab92e: FITCC_TDC_UTILITY::FITCC_TDC_UTILITY + 0x16e (FITTER_FITCC) 0x4358a: FITCC_ENV::get_tdc_utility_or_create_if_necessary + 0x57a (FITTER_FITCC) 0x420ac: FDRGN_EXPERT::do_post_finalize_hold_fixing + 0x1d4c (fitter_fdrgn) 0x43c62: FDRGN_EXPERT::do_post_finalize_ops + 0x422 (fitter_fdrgn) 0x4c4cc: FDRGN_EXPERT::finalize + 0x15cc (fitter_fdrgn) 0x16e8a: fit2_fit_finalize_auto + 0xba (comp_fit2) 0x16442: TclNRRunCallbacks + 0x62 (tcl86) 0x3a89: fit2_fit_finalize + 0x369 (comp_fit2) 0x16442: TclNRRunCallbacks + 0x62 (tcl86) 0x17c4d: TclEvalEx + 0x9ed (tcl86) 0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86) 0xa5136: Tcl_EvalFile + 0x36 (tcl86) 0x11fac: qexe_evaluate_tcl_script + 0x2cc (comp_qexe) 0x11215: qexe_do_tcl + 0x345 (comp_qexe) 0x1671e: qexe_run_tcl_option + 0x5ee (comp_qexe) 0x26711: qcu_run_tcl_option + 0xc61 (comp_qcu) 0x1601b: qexe_run + 0x3ab (comp_qexe) 0x170e4: qexe_standard_main + 0xe4 (comp_qexe) 0x1f72: qfit2_main + 0x82 (quartus_fit) 0x13e58: msg_main_thread + 0x18 (CCL_MSG) 0x1516e: msg_thread_wrapper + 0x6e (CCL_MSG) 0x1f900: mem_thread_wrapper + 0x70 (ccl_mem) 0x1348e: msg_exe_main + 0xae (CCL_MSG) 0x2838: __scrt_common_main_seh + 0x11c (quartus_fit) 0x13033: BaseThreadInitThunk + 0x13 (KERNEL32) 0x73690: RtlUserThreadStart + 0x20 (ntdll) End-trace Executable: quartus_fit Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 18.1.0 Build: 222 Edition: Pro Edition
  • WGith's avatar
    WGith
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago
    Windows 10 Pro OS 1 TB SSD hard drive
  • skyjuice's avatar
    skyjuice
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    It seems to be related to port connection. Would you be able to share your project?