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MicroDick's avatar
MicroDick
Icon for New Contributor rankNew Contributor
2 years ago

clock control intel FPGA IP is not correct

I have created a project in quartus prime pro 23.4 ant I have used clock control intel FPGA IP as a MUX for clock.And When I run synthesis error encouted. Error(13224): Verilog HDL or VHDL error at cl...
EthanLi's avatar
EthanLi
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi,


The pof file contains the device and the information of the quartus version.

The rpd or rbf file could be the row data.

But I don't think it is possible to get the configuration file by this way.

Thanks,

Ethan