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MicroDick
New Contributor
New Contributorclock control intel FPGA IP is not correct
I have created a project in quartus prime pro 23.4 ant I have used clock control intel FPGA IP as a MUX for clock.And When I run synthesis error encouted. Error(13224): Verilog HDL or VHDL error at cl...
sstrell
Super Contributor
Super ContributorThis formatting is terrible, but you have clkselect as a single bit input yet you're using it as a 2 bit input.
