Occasional Contributor
You may checkout the forum post here:
It seems for these very low frequencies you just lie. R
Reference:
Best Regards,
Richard Tan
Super ContributorFirst, why don't you just use the PLL to generate all these clocks? Are you using the other clock outputs or have no PLL available for doing this?
Also, don't use get_nets. You should be using get_pins to target physical points in the netlist. Did you use the Name Finder to make sure you have the correct target names? I'm guessing the names shown in this report showing as unconstrained should be the names you should be using in your constraints, but you must use the Name Finder to verify.
In the report, those two clock inputs are showing as unconstrained base clocks because your clock constraints are incorrect. The unconstrained paths report indicates that it thinks these are base clocks that need clock constraints.
Occasional ContributorThanks for your reply.
Then I pointed the source and the target with pin in my sdc file. But I got the same result as before.
create_clock -period 20.833 [get_ports {FPGA_CLK1}]
create_clock -period 68.817 [get_ports {FPGA_CLK2}]
derive_pll_clocks
derive_clock_uncertainty
#create_generated_clock -name PLS1r57ms -source [get_pins {SLOWCLK_1|cnt1|count[0]|clk}] -divide_by 15700 [get_pins {SLOWCLK_1|cnt1|count[13]|q}]
create_generated_clock -name PLS1r57ms -source [get_pins {PLL_inst|altpll_component|auto_generated|pll1|clk[0]}] -divide_by 15700 -duty_cycle 0.478 [get_pins {SLOWCLK_1|cnt1|count[13]|q}]
create_generated_clock -name PLS7r85ms -source [get_pins {SLOWCLK_1|cnt1|count[13]|q}] -divide_by 5 -duty_cycle 0.2 [get_pins {SLOWCLK_1|cnt2|count[2]|q}]
#create_generated_clock -name PLS7r85ms -source [get_nets {SLOWCLK_1|cnt1|count[13]}] -divide_by 5 -duty_cycle 0.2 [get_nets {SLOWCLK_1|cnt2|count[2]}]
create_generated_clock -name PLS94r2ms -source [get_pins {SLOWCLK_1|cnt2|count[2]|q}] -divide_by 12 -duty_cycle 0.33 [get_pins {SLOWCLK_1|cnt3|count[3]|q}]
#create_generated_clock -name PLS94r2ms -source [get_nets {SLOWCLK_1|cnt2|count[2]}] -divide_by 12 -duty_cycle 0.33 [get_nets {SLOWCLK_1|cnt3|count[3]}]
I always use the name finder to point sources and targets. Without it it is quite tough to know correct pin or net names.
Frequent ContributorWhy are you using BOTH derive_pll_clocks and create_generated_clocks ?
Either let Quartus do it (first option) or you do it manually (second option).
For example, I have a design with a couple of clocks generated based on a 50MHz clock input to the PLL.
The PLL generates one clock CPUCLK at 80MHz, and a second clock based on logic divide of the PLL output RTCCLK at 25KHz.
# Master 50MHz clock input create_clock -period 20.0 -name CLOCK_50 [get_ports {CLOCK_50}] # Created clocks based on PLLs (CPUCLK = 80MHz) create_generated_clock -source {pll|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50 -name CPUCLK {pll|altpll_component|pll|clk[0]} # Created clocks based on logic (RTCCLK = 25KHz) create_generated_clock -source {pll|altpll_component|pll|clk[0]} -divide_by 5000 -duty_cycle 50 -name RTCCLK {dk8ea_clock:rtc|rtcclk}
Super Contributorderive_pll_clocks only works for the PLL. They have to create generated clocks for those additional ones based on the PLL output.
As I mentioned in my first reply, OP should just put all the clocks in the PLL if they can, but I know MAX 10 is limited with PLLs so maybe that's not an option.
