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Altera_Forum
Honored Contributor
10 years agoCLOCK_50 was determined to be clock but was found without an associated clock assign.
Hello, I am having an issue in combining two clocks signals in one project. I am using DE2 Altera board. I am also using Nios processor. So, basically I am trying to merge to independently ...
Altera_Forum
Honored Contributor
10 years agoHave you made a constraints (.sdc) file? If not you will need to in order to tell Quartus what clocks you have and at what frequency.
An example minimal SDC file would be the following:
set_time_format -unit ns -decimal_places 3
# ############################################################################## Create Input reference clocks
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 }
# ############################################################################## Now that we have created the custom clocks which will be base clocks,# derive_pll_clock is used to calculate all remaining clocks for PLLs
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty