Cleaning up latch warnings

I am trying to build an SPI interface on a Max II device. I want to latch the shift-register data into my control bits when CS is low, like this:

reg shift = 0;
always @(posedge sclk)
  if (cs)
    shift <= {shift, sin};
reg run, busy, mode;
always @*
  if (!cs)
  begin
    run = shift;
    busy = shift == 2'b11 || shift == 2'b10;
    mode = shift == 2'b11;
  end

This code produces exactly the logic I want when I check its output in the RTL viewer. The problem is that my build log is full of warnings like these:

--- Quote Start ---

Warning (10240): Verilog HDL Always Construct warning at spi.v(66): inferring latch(es) for variable "run", which holds its previous value in one or more paths through the always construct

--- Quote End ---

--- Quote Start ---

Warning: Timing Analysis is analyzing one or more combinational loops as latches

--- Quote End ---

I come from a software development background where the goal is to have a warning-free build. Is there any way to tell Quartus, "Yes, I really do want latches here. Please don't warn me about this anymore?" That way, if I really do create an unintended latch later on in the project, the real warning doesn't get lost in the noise.

Maybe latches are frowned upon on these chips, and I should use edge-triggered registers instead? I can get rid of most of them, but there are a few places where I really and truly do need latches to avoid timing glitches.