Classic Timing Analyzer: tsu calculation backwards?

tsu, th, tco, and min tco constraints in Quartus and the report tables for these are always for I/O timing at device pins and are in terms of the timing right at the data pin with respect to the timing right at the clock pin, not right at the register inside the FPGA.

You will see things like micro tsu and micro th for the registers inside the device when you look at the list-paths details, but you don't constrain things like tsu for the internal registers. For internal timing, you enter fmax constraints (which will be done automatically for you for PLL clocks with the Classic Timing Analyzer), clock uncertainty, multicycle, and false paths ("Cut Timing Path" in the Classic Timing Analyzer).