Classic Timing Analyzer: tsu calculation backwards?

It's probably easier to understand if you break out the data and clock paths. Your Tsu result is not saying the data is available 3.7sn before the clock(it has no idea when the clock and data come into the device). It's saying that if you don't have data available at the FPGA data port 3.7ns before the clock is available, your interface will fail. The smaller that Tsu result is, the easier your requirement becomes on the external world. So a 0.5ns requirement is pretty tight, and you're not making it.