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Hi,
in your post you mentioned that you have a clock in your design available. That's good,
because you can develop a synchronous design. Have a look to the small project I have attached. Is that the function you would like to implement ?
Kind regards
GPK
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Awesome, thanks for your response! At first I wanted to have these storage elements working asynchronous, but I guess I'll focus on having everything working synchronous, which will probably save time for debugging. But is it okay and synchronous design then, to lead back the output of the Flipflop to the Enable-Input of the FF? I negated the reset input, but otherwise it's just what I needed. Thanks!
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Hi,
I forgot to answer your first question. The input and output constraints depend on the circuit which drives the FPGA ( when are the data stable in relation to the clock) and
the timing requirements of the circuit which is driven by the FPGA ( when must be the
output data of the FPGA stable in relation of the clock of the receiving circuit).
Kind regards
GPK
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I still don't know whether I understood it correctly: So I pass the Timing Analysis Tool the constraints of the signals which enter the CPLD-Design (Input ports) and which leave the CPLD (Outputs) to the PCB and I make sure that these signals work fine with the Setup & Hold-Times of the CPLD. Sorry, if my assumptions seem stupid. I am trying really hard to comprehend what goes on within and outside the CPLD. Greetings!
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