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Altera_Forum's avatar
Altera_Forum
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12 years ago

Check two different clocks

I have two clock signals: clock_50 (50MHz) and clock (16kHz). Now I want FPGA to do three commands within each clock (16kHz), the commands are done in one clock_50 (50MHz).

I tried but it doesn't work. The idea is the same following lines, but I dont know how to code it 

always @(posedge clock) begin
     always @(posedge clock_50) begin
         //do a command
         //do a command
         //do a command
     end
end

Could you please help me?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You should consider only the 50MHz faster signal as the 'real' clock.

    Use a single always @(posedge clock_50) . Inside this process latch the 16kHz signal into a register and whenever you spot a change to state high trigger your 3 command sequence.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thank you for your reply.

    But I want to generate 3 sub-clocks . I tried 

    always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin // reset the registers
		count = 0;
	end else begin
		count_cal = 5'b00000; // reset
	end
end
always @(posedge clk_50 or negedge rst_n) begin
	if (!rst_n) begin // reset the registers
		flag_cal = 0;
		count_cal = 0;
	end else begin
		if (clk) begin
			count_cal = count_cal + 5'b00001;
			if ((count_cal > 1) && (count_cal < 7)) //
				flag_cal <= flag_cal + 1'b1;
			else
				flag_cal <= 1'b0;
		end
	end
end
		
always @(posedge flag_cal or negedge rst_n) begin
// this is to do 3 commands

    However it cannot elaborate successfully.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    @Cris72

    As you said I just do some commands within a hafl of clock cycle, not within the whole clock cycle