Thank you for your reply.
But I want to generate 3 sub-clocks . I tried
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin // reset the registers
count = 0;
end else begin
count_cal = 5'b00000; // reset
end
end
always @(posedge clk_50 or negedge rst_n) begin
if (!rst_n) begin // reset the registers
flag_cal = 0;
count_cal = 0;
end else begin
if (clk) begin
count_cal = count_cal + 5'b00001;
if ((count_cal > 1) && (count_cal < 7)) //
flag_cal <= flag_cal + 1'b1;
else
flag_cal <= 1'b0;
end
end
end
always @(posedge flag_cal or negedge rst_n) begin
// this is to do 3 commands
However it cannot elaborate successfully.