CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized

Bottom line:
I don’t understand the suggested solution.

The places you edited are synchronizers. As a synchronizer, the intention is to put one FF on the source clock domain and two FFs on the target clock domain, as it is in the original design (see the first picture below).
In the instance die_ready_Z, the first FF is on the clock domain of pll_clk and it is only one FF. The next two FFs are on the clock which arrives from the DIB dib_rx_data_2_18_in_i_0_0 (the target clock domain).
You will see that the Q (output) of sync2_in is going to FFs which use the same clock domain (dib_rx_data_2_18_in_i_0_0). I didn’t include this in the picture as it complicates the view.
I don’t understand the solution you described (see the second picture). You switched clocks? Why? This does not sync it to the target clock domain.
Bottom line: This thread is about recognizing synchronizers. I don’t understand from your solution why Quartus didn’t recognize these standard synchronizers and why I need to adopt your solution.

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