"case statement choices must cover all possible values of expression."

With VHDL std_logic_vector type, there are other levels besides 0 and 1, mostly used for simulation.

I'm guessing that the code included in the download for the dev kit is from an older version of the software. Pro edition synthesis is stricter than the standard edition on certain things and this might be part of that if this older code was designed for Standard edition (Arria 10 is the only device family supported in both Standard and Pro). You could either try editing the code (when OTHERS => av_data_read <= product;) or try compiling in the Standard edition of the software.