Case don't care statement won't work

Ok i did it but I have an issue where I can't use portion of the case as an assignment operator. For example:

when "111---" =>
mult_divide_bus_out0 <= a_bus_in;
mult_divide_bus_out1 <= b_bus_in;
mult_divide_instruction_bus_out <= instruction(2 downto 0);

Does not create anything during the simulation (simulation software is Modelsim free altera version)

I am wondering if I can do this or if it is not allowed.

Edit: I figured out a way to bypass the issue. I had to create another signal and assign the input instruction to the new signal. Then I have to use the new signal instead of the old one to output .