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Altera_Forum's avatar
Altera_Forum
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13 years ago

Case don't care statement won't work

Hello, I am wondering why I am getting an error when using a don't care statement in a case. Here is a portion of the code: 


when "1000--" =>
add_bus_out0 <= a_bus_in;
add_bus_out1 <= b_bus_in;
subtract_out <= instruction(1);
unsigned_add_out <= instruction(0);
when "100100" =>
and_bus_out0 <= a_bus_in;
and_bus_out1 <= b_bus_in;
when "1001-1" =>
or_bus_out0 <= a_bus_in;
or_bus_out1 <= b_bus_in;
negate_or_out <= instruction(1);
when "100110" =>
xor_bus_out0 <= a_bus_in;
xor_bus_out1 <= b_bus_in;

This is the error message I get: 


Warning (10325): VHDL Choice warning at testvhdl.vhd(294): ignored choice containing meta-value ""1000--""
Warning (10325): VHDL Choice warning at testvhdl.vhd(302): ignored choice containing meta-value ""1001-1""

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Hello, I am wondering why I am getting an error when using a don't care statement in a case. Here is a portion of the code: 

    
when "1000--" =>
<snip>

    This is the error message I get: 

    
Warning (10325): VHDL Choice warning at testvhdl.vhd(294): ignored choice containing meta-value ""1000--""
Warning (10325): VHDL Choice warning at testvhdl.vhd(302): ignored choice containing meta-value ""1001-1""

    --- Quote End ---

    Comparing something directly with the don't care either with an equals (i.e. this = "100--") or with a 'with' as you've done or as part of a case statement won't give you what you want. The only way is to either not include the bits in the comparison at all (which sometimes cannot be done) or the comparison must be done with the std_match function. For that you would say something like 

     
if std_match(this, "100--") then

    That's the way the std_logic_1164 package rolls.

    Kevin Jennings
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    This is actually part of VHDL 2008, and should be something that Quartus supports. Make sure you have the code version set to VHDL 2008. If you still get an error when you've selected this mode, raise a support request (as according to their documentation they support it).

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    This is actually part of VHDL 2008, and should be something that Quartus supports. Make sure you have the code version set to VHDL 2008. If you still get an error when you've selected this mode, raise a support request (as according to their documentation they support it).

    --- Quote End ---

    I changed the version of VHDL to 2008 by changing the properties of the VHDL file, however I still have the compiling errors. Do I have to change something else in order for it to work.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Case with don't care does work in Quartus 12. The warning suggests that you forget to write case? instead of case. 

    case? request is
when "1---" => grant <= "1000";
when "01--" => grant <= "0100";
when "001-" => grant <= "0010";
when "0001" => grant <= "0001";
when others => grant <= "0000";
end case?;
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Case with don't care does work in Quartus 12. The warning suggests that you forget to write case? instead of case. 

    case? request is
when "1---" => grant <= "1000";
when "01--" => grant <= "0100";
when "001-" => grant <= "0010";
when "0001" => grant <= "0001";
when others => grant <= "0000";
end case?;

    --- Quote End ---

    Ok I will try that out. The only issue is that I am using Quartus 11.1 currently, but I will figure out soon if it matters.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Ok i did it but I have an issue where I can't use portion of the case as an assignment operator. For example: 

    
when "111---" =>
mult_divide_bus_out0 <= a_bus_in;
mult_divide_bus_out1 <= b_bus_in;
mult_divide_instruction_bus_out <= instruction(2 downto 0);

    Does not create anything during the simulation (simulation software is Modelsim free altera version)

    I am wondering if I can do this or if it is not allowed.

    Edit: I figured out a way to bypass the issue. I had to create another signal and assign the input instruction to the new signal. Then I have to use the new signal instead of the old one to output .