Carry_sum

wow. do you understand the architecture of logic element? if no please read about it.

The 'CIN' cannot fed up with signal you provide. it is stored in configuration. Am I wrong?

So in you code the very first 'cin' is used in the 2nd LE and in the very last LE you have no 'cout'.

i can mistake but it seems you can use '1' or '0' on 'cin' in the very first LE in your chain. but you should provide code that syntethis tool can aware for such situation.

--- Quote Start ---

wow. do you understand the architecture of logic element? if no please read about it.

The 'CIN' cannot fed up with signal you provide. it is stored in configuration. Am I wrong?

So in you code the very first 'cin' is used in the 2nd LE and in the very last LE you have no 'cout'.

i can mistake but it seems you can use '1' or '0' on 'cin' in the very first LE in your chain. but you should provide code that syntethis tool can aware for such situation.

--- Quote End ---

Yes i know about it. i was trying to understand what is the best primitive to be used in Cyclone2 for the TDC.

why not use instances of dedicated LPM-? they take care for you.

How do you determine 'best'? by Fmax or by number of LE or by power consumption?

As for me I don't want to use primitives directly, all you can get comes from written code and assignments.

after all why not to consider 'Design Space Explore' ?

i would like to know what is the right way to create a chain structure in the FPGA trying to reduce as soon as i can the ultra wide bins.

:)

oh dear

library
	ieee;
use
	ieee.std_logic_1164.all,
	ieee.numeric_std.all;
	
	
entity counter is
	generic(
		DATA_WIDTH : positive := 4
	);
	port(
		aclr,		-- general asynchronus reset
		clk,		-- general synchronous clock
		
		sat_in	-- previous counter saturated
			: IN std_logic;
		
		o 			-- counter output value
			:	OUT unsigned(DATA_WIDTH - 1 downto 0);
		
		sat_out	-- the counter is saturated with all ones
			: OUT std_logic
	);
end counter;
architecture v1 of counter is
	constant sat_cond : unsigned(DATA_WIDTH - 1 downto 0) := (0 => '0', others => '1');
	signal cnt : unsigned(DATA_WIDTH - 1 downto 0);
begin
	
	process(aclr, clk)
	begin
		if aclr = '1' then
			cnt <= (others => '0');
			sat_out <= '0';
		elsif rising_edge(clk) then
			if sat_in = '1' then
				cnt <= cnt + 1;
			end if;
			if sat_in = '1' then
				if cnt = sat_cond then -- plan output value in advance
					sat_out <= '1'; 
				else 
					sat_out <= '0';
				end if;
			end if;
		end if;
	end process;
	
	o <= cnt;
	
end v1;

try this counter with differnt DATA_WIDTH value

oh , you can use cover for this

library
	ieee;
use
	ieee.std_logic_1164.all,
	ieee.numeric_std.all,
	work.all;
entity CountersTop is
	generic(
		DATA_WIDTH : positive := 64; -- counter width
		N : positive := 4 -- number of slices
	);
	port(
		r, clk, cu_in : IN std_logic;
		o : OUT unsigned(DATA_WIDTH - 1 downto 0);
		cu_out : OUT std_logic
	);
end CountersTop;
architecture rtl of CountersTop is
	signal internal_cu : std_logic_vector(N - 1 downto 0);
	constant slice : positive := DATA_WIDTH / N;
begin
	cntrs : 
	for i in 0 to N - 1 generate
		first : if i = 0 generate
		cnt1: 
			entity counter(v1)
			generic map(
				DATA_WIDTH => slice
			)
			port map(
				aclr => r,
				clk => clk,
				sat_in => cu_in,
				o => o((I + 1) * slice - 1 downto I * slice),
				sat_out => internal_cu(i)
			);
		end generate first;
		follow : if i > 0 generate
		cntX:
			entity counter(v1)
			generic map(
				DATA_WIDTH => slice
			)
			port map(
				aclr => r,
				clk => clk,
				sat_in => internal_cu(i-1),
				o => o((I + 1) * slice - 1 downto I * slice),
				sat_out => internal_cu(i)
			);
		end generate follow;
	end generate cntrs;
	
	cu_out <= internal_cu(N - 1);
	
end rtl;

find your DATA_WIDTH and N that conforms you