Carry_sum

oh dear

library
	ieee;
use
	ieee.std_logic_1164.all,
	ieee.numeric_std.all;
	
	
entity counter is
	generic(
		DATA_WIDTH : positive := 4
	);
	port(
		aclr,		-- general asynchronus reset
		clk,		-- general synchronous clock
		
		sat_in	-- previous counter saturated
			: IN std_logic;
		
		o 			-- counter output value
			:	OUT unsigned(DATA_WIDTH - 1 downto 0);
		
		sat_out	-- the counter is saturated with all ones
			: OUT std_logic
	);
end counter;
architecture v1 of counter is
	constant sat_cond : unsigned(DATA_WIDTH - 1 downto 0) := (0 => '0', others => '1');
	signal cnt : unsigned(DATA_WIDTH - 1 downto 0);
begin
	
	process(aclr, clk)
	begin
		if aclr = '1' then
			cnt <= (others => '0');
			sat_out <= '0';
		elsif rising_edge(clk) then
			if sat_in = '1' then
				cnt <= cnt + 1;
			end if;
			if sat_in = '1' then
				if cnt = sat_cond then -- plan output value in advance
					sat_out <= '1'; 
				else 
					sat_out <= '0';
				end if;
			end if;
		end if;
	end process;
	
	o <= cnt;
	
end v1;