Carry Look-Ahead Counter

Hello,

a synchronous counter inferred from an expression like CNT <= CNT + 1 can't but using carry look-ahead to my opinion. You specify the behaviour, the FPGA compiler has to know how-to.

Regards,

Frank

Please help - The complete code (*hdl - example )is necessary to me.

Synchronous 24 bit Carry Look-Ahead Counter.

Hello,

the point is that Quartus synthesis claims to handle the optimization of carry chains internally and not to bother the user with details. In most cases Quartus synthesis ends up in a continous "ripple" carry chain through all counter bits cause it's fast enough. The said 24 bit binary counter performs above 300 MHz with MAX II for example.

At the lpm* Megafunction level, there are additional parameters controlling carry chain synthesis, but I never used them, may be someone can tell about. I also don't know, if this option would be always used by Altera synthesis where appropriate.

As I told, I'm used to infer all counters from HDL statements. I found, that for a simple up counter typically a lpm_add function is instantiated rather than a lpm_counter, but that should make no big difference. I also noticed, that Altera often uses lpm_counter Megafunction for counters internal to their IP cores, but I actually don't know if this brings any benefit.

When achieving complex signal processing functions in FPGA, I'm happy not to care about synthesis details of counters - if it performs fast enough.

Best regards,

Frank