Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I have tested TDC. Only thing I was doing wrong were START and STOP blocks which caused usage of strange paths. So here is how I test delay line. I am using dynamic phase configuration in PLL. I have two signals from PLL. First one is START signal and it is connected directly to Carry in at the beginning of delay line. Phase shifted signal is used for latching FF's. I was changing phase with step of 100 ps. I was watching output of first 8 adders in delay line on LEDs. Every increase of phase step caused propagation through two adders which means that resolution is around 50 ps.