Can't use .SDC Example file without errors

Hi,

I am very new to this and trying to compile an application for an EPM7128S (yes, I know, it's very old).

The compilation goes OK, but I was getting warnings that TimeQuest could not analyse the design because there was no constraints file present.

After a bid of searching, I found the example .SDC file on the Altera website, containing the lines :-

# constrain clock port clk with a 10-ns requirement

create_clock -period 10 [get_ports clk]

# automatically apply a generate clock on the output of phase-locked loops (plls)# this command can be safely left in the sdc even if no plls exist in the design

derive_pll_clocks

# constrain the input i/o path

set_input_delay -clock clk -max 3 [all_inputs]

set_input_delay -clock clk -min 2 [all_inputs]

# constrain the output i/o path

set_output_delay -clock clk 2 [all_outputs] 2

According to the web page, this basic example should be able to work on all designs.

I was getting errors for a couple of LPM_counter modules that I had not declared as clocks, so I added the command

"derive_clocks " which I think should find undeclared clocks?

Anyway, with, or without the modification that I made, the compile fails with the following errors for the .sdc file

Error (332000): More than 2 positional arguments specified: 2, _col4, 2

---------------------------------------------------------------------------

Usage: set_output_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>

-h | -help: Short help

-long_help: Long help with examples and possible return values

-add_delay: Create additional delay constraint instead of overriding previous constraints

-clock <name>: Clock name

-clock_fall: Specifies output delay relative to the falling edge of the clock

-fall: Specifies the falling output delay at the port

-max: Applies value as maximum data required time

-min: Applies value as minimum data required time

-reference_pin <name>: Specifies a port in the design to which the output delay is relative

-rise: Specifies the rising output delay at the port

-source_latency_included: Specifies input delay already includes added source latency

<delay>: Time value

<targets>: Collection or list of output ports

---------------------------------------------------------------------------

while executing

"set_output_delay -clock clk 2 [all_outputs] 2"

(file "MTXPlus_CPU.sdc" line 22)

Can anyone tell me where I've gone wrong please?

regards

Dave