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Norick's avatar
Norick
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7 years ago

Can't route signal to atom for simple ADC PLL

Hello I am using: Max10 10M40DAF256I7G Quartus 18.0 Here, I am using a PLL with 2MHz output (Intel ALTPLL) followed by ClockControlBlock which feeds the input of the Max10 internal ADC at the e...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Why don't you try using Qsys yo build your Dual ADC system and then have a PLL external to the Qsys system as shown in this desgin. This simple Dual ADC design compiles without any issues.

  • Norick's avatar
    Norick
    Icon for New Contributor rankNew Contributor
    7 years ago

    I think I have found the problem now. What I am using is a PLL followed by a Clock-ControlBlock which goes to the ADC. It looks like this:

    When this Clock-ControlBlock is deleted it works. The reason for this Clock-ControlBlock is to disable the ADC PLL when not used.

    Question:

    • How would you enable/disable such ADC PLL Clock?

    Thanks