Can't route signal to atom for simple ADC PLL

Very good input Abe and I checked the solutions with my issue. Intel writes following statement to the ADC/PLL clock source (2.1.5 ug_m10_adc):

The ADC block uses the device PLL as the clock source. The ADC clock path is a dedicated clock path. You cannot change this clock path. Depending on the device package, the Intel MAX 10 devices support one or two PLLs—PLL1 only, or PLL1 and PLL3.

For devices that support two PLLs, you can select which PLL to connect to the ADC. You can configure the ADC blocks with one of the following schemes:

• Both ADC blocks share the same clock source for synchronization.

• Both ADC blocks use different PLLs for redundancy.

I use a dual ADC configuration with a single PLL for the ADC. The clock source to the ADC PLL is CLK1p (Pin K6) which is the input for PLL1 and PLL3 of the Max10. Below the input CLK1 with the PLL_ADC_intern and a ClockControlBlcok. The output goes to the Max10 dual ADC.

Question:

• Do I need to tell which PLL I am unsing for the ADC? According the Intel manual (see above) it says "you can select which PLL to connect to the ADC." Where can I do that?

Thanks