Can't perform simulation of IP file because no simulation model files were detected

It seems like altera forum limits and crops my file size (therefore photo size) to save server disc space.

I have uploaded the screenshot to https://i.imgur.com/mharvjq.png

Just to say that I have included PCIeGen2x8If128_core.vo IP functional simulation model file, yet I am still getting the following error:

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Error: Error: Can't perform simulation of IP file /home/phung/Documents/fpga_overlay/riffa/fpga/altera/de4/DE4Gen2x8If128/ip/PCIeGen2x8If128_core.v because no simulation model files were detected

Error: Error: You did not generate the simulation model files or you generated the IP file using an older version of Intel FPGA IP which is not supported by RTL NativeLink Simulation

Error: Error: Regenerate the IP and simulation model files using the latest version of Intel FPGA IP for RTL NativeLink Simulation flow to function correctly

Error: Error: NativeLink simulation flow was NOT successful

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