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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Can't instantiate Signal Tap using megafunction tool in Quartus 17.0.1

I am attempting to instantiate a signal tap core using the megafunction flow. Quartus generates the IP but when I instantiate it in my project and compile I get the following error. Error(1378...
SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I having this same error in quartus 18.0, and the suggestions here have not solved it. Is there anything else I should try?

designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

When generating the IP make sure to chose Verilog as the output. The module can be instantiated as either Verilog or VHDL but when generating the IP, if choosing VHDL instead of Verilog as the output I get this error. Using Verilog as output fixed the issue for me.