Can't instantiate Signal Tap using megafunction tool in Quartus 17.0.1

Attached is my code. I followed the tips posted here, but I get these errors:

Error(13785): VHDL Use Clause error at signaltap.vhd(47): design library "altera_signaltap_ii_logic_analyzer_180" does not contain primary unit "sld_signaltap" 
Error(13827): Ignored construct rtl at signaltap.vhd(76) due to previous errors 
Error(13806): VHDL syntax error at stratix10Test_top.vhd(44) near text ; 
Error(13806): VHDL syntax error at stratix10Test_top.vhd(51) near text variable 
Error(13806): VHDL syntax error at stratix10Test_top.vhd(57) near text elsif 
Error(13806): VHDL syntax error at stratix10Test_top.vhd(59) near text if 
Error(13806): VHDL syntax error at stratix10Test_top.vhd(61) near text if 
Error(13806): VHDL syntax error at stratix10Test_top.vhd(69) near text if 
Error(13806): VHDL syntax error at stratix10Test_top.vhd(71) near text if 
Error: Flow failed:  
Error: Quartus Prime Synthesis was unsuccessful. 10 errors, 0 warnings 
	Error: Peak virtual memory: 1137 megabytes 
	Error: Processing ended: Wed Feb  6 14:40:56 2019 
	Error: Elapsed time: 00:00:12 
	Error: Total CPU time (on all processors): 00:00:12 

I think the 'Error (13806)' messages are from quartus not knowing what to do after the signaltap instance fails.

Strangely, I get this error if the signaltap .ip file is included in the quartus project, even if it's not instantiated in the top module..