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Altera_Forum's avatar
Altera_Forum
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12 years ago

can't infer register because its behavior depends on the edges of multiple clock

Hi

i wrote this vhdl code in Quartus II version 7.2 but when i want to compile it this error is displayed

can't infer register for flag because its behavior depends on the edges of multiple distinct clocks

i sure this code true because i wrote this code in modelsim software and xilinx-ise and simulated . it worked properly

what is wrong ?

please help me

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity delay is

port(

clk :in std_logic;

change :in std_logic;

output :out std_logic

);

end delay;

architecture behavior of delay is

signal flag : std_logic;

signal counter :integer range 0 to 100000;

begin

----------------------------

process(change, clk)

begin

if(rising_edge(change))then

flag <= '1';

output <= '0';

counter <= 0;

else

if(rising_edge(clk))then

if(flag = '1')then

if(counter < 100000)then

counter <= counter + 1;

output <= '0';

else

output <= '1';

flag <= '0';

end if;

end if;

end if;

end if;

end process;

---------------------------

end behavior;

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi abbasi,

    you are trying to make conditions with two edges : "clk" and "change" !

    This is not proper and may be this is what the tool can't synthetize.

    regards,
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Yes exactly. This code works well in a simulator, but not in a synthesizer because the FPGA hardware can't do what you are describing. A clocked process can only depend on the edge of a single clock, just as a FPGA hardware register only has one clock input.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi thank you for your attention.

    i want to enable counter with "change" signal and increase counter with clk rising_edge

    and when "change" signal enabled again reset the counter and output signals.

    in other hand i want to build a delay for output in code when change signal is enable for one clock.

    but i dont know different code from this

    how should i do this ?

    please help me..

    all the best for you..
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    The usual way to do this is to clock your process only on the rising edge of the "clk" signal, and sample your "change" signal in a register. You can call the sampled signal "prev_change" for example. Then you can compare the previous and the current value of the signal. If "prev_change" is '0' and "change" is '1' then you know you had a rising edge on "change".

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi

    I wrote this code in Quartus and simulate it. it was worked very well

    thank you very much

    entity delay is

    port(

    clk :in std_logic;

    change :in std_logic;

    output :out std_logic

    );

    end delay;

    architecture behavior of dead_band_generation_logic is

    signal flag : std_logic;

    signal flag_a : std_logic :='1';

    signal counter :integer range 0 to 100000;

    signal prev_change :std_logic ;

    begin

    ---------------------------

    process(clk)

    begin

    if(falling_edge(clk))then

    if(flag_a = '1')then

    prev_change <= change;

    flag_a <= '0';

    elsif(flag_a = '0')then

    if(prev_change = '0' and change = '1')then

    flag <= '1';

    counter <= 0;

    output <= '0';

    end if;

    end if;

    if(flag = '1')then

    if(counter < 25)then

    counter <= counter + 1;

    output <= '0';

    else

    output <= '1';

    flag <= '0';

    end if;

    end if;

    end if;

    end process;

    --------------------------

    end behavior;