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Altera_Forum's avatar
Altera_Forum
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17 years ago

cant get one-hot with VHDL in quartus II 8.1

Can anyone help me with implementing a one-hot state machine in quartus II 8.1 with VHDL.

I created a simple test file and set the state machine processing to one-hot in 'More Analysis and Synthesis Settings'

When I go to simulate, the node finder gives me four registers for the four states, but one of the states remains undefined, and the encoding appears to be a combination type like grey or johnson.

Also tried an enumerated encoding which didnt work either.

I attached the code I was trying to use.

Thanks in advance for any help.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    In your example code, the FSM attributes must be deleted, to make Quartus recognize a state machine. But then it's synthesized in one-hot style, also in default auto mode.

    I guess, you didn't consider, that the s1 state bit is always inverted, so that an all zero state vector corresponds to initial state s1.