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- Altera_Forum
Honored Contributor
Hi,
How many clocks are u using in your design?Maybe you have no more global line...Are u using ALTCLKCTRL megawizard?
Hi,
I've encounterred with this promblem.I use the ep2c8 ,design with 2 plls.quartus give me an error "Can't fit <clk0> fan-out of node into a single clock region",where clk0 is the 50MHz output of one pll This is my 1st time seeing this error,What should i do?Hi,
How many clocks are u using in your design?Maybe you have no more global line...Are u using ALTCLKCTRL megawizard?