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Honored Contributor
Honored ContributorCan't fit design in device after upgrade from 13.0SP1 to 13.1
Hi,
I have a project for the MAX V "5M240ZM100C5" CPLD, almost at the max capacity of the device. Previously I was using 32bit PC, Windows 7 and Quartus II 13.0 SP1 Web Edition, and was able to successfully compile and fit the design on the device. Here is a piece of the log from the Fitter:
Info: Running Quartus II 32-bit Fitter Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
...
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off InterfaceLogic -c InterfaceLogic
Info: qfit2_default_script.tcl version:# 1
...
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
...
Info (332144): No user constrained base clocks found in the design
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info (332127): Assuming a default timing requirement
Info (332111): Found 5 clocks
...
Info (186079): Completed User Assigned Global Signals Promotion Operation
...
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186391): Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
Info (170216): Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements
Info (176234): Starting register packing
Info (186391): Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
Info (170216): Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements
Info (176234): Starting register packing
Info (186391): Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 28% of the available device resources
Info (170196): Router estimated peak interconnect usage is 28% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info (11888): Total time spent on timing analysis during the Fitter is 0.55 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
...
Info: Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings
Info: Running Quartus II 64-Bit Fitter
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
...
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off InterfaceLogic -c InterfaceLogic
Info: qfit2_default_script.tcl version:# 1
...
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
...
Info (332144): No user constrained base clocks found in the design
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info (332127): Assuming a default timing requirement
Info (332111): Found 5 clocks
...
Info (186079): Completed User Assigned Global Signals Promotion Operation
...
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (170189): Fitter placement preparation operations beginning
Error (170011): Design contains 178 blocks of type logic cell. However, the device contains only 160 blocks.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
