Hi everyone, i am using DE0-nano cyclone IV E. Basically im using the LEDs to signal whether i have over counted. I do not know what is wrong but my integer range doesn't seem to limit the count, and my resetting code isn't preventing the count from over counting. Please refer to the attached file for the code. Its the 2nd process. I am new to quartus II and vhdl, please do pardon me if the mistake is obvious.

basically, i need the counter to be counting correct as i am trying to implement my code for ADC usage, which uses SPI and its vital that the counting cycle is correct. Thank you all.

How are you testing the design (Modelsim, Signaltap) and what do you exactly observe? Apart from possible other problems, it should be mentioned that the ripple clock generation scheme is bad style and shouldn't be used for real hardware designs.

Unfortunately, I tried modelsim but without much help and mostly vague guides online, I can't seem to get it to work. Basically, I'm using the LED as an indication to over counting. I'm sorry, what do you mean by ripple clock generation scheme? I'm using the de0 nano for adc as well as a square wave generator.

A ripple clock is a clock that is generated via logic - ie. exactly what you have done - used a counter to create a slower clock from a faster one. It is better practice to use the same clock over the whole system and generate clock enables to only enable the target at the given rate. So to divide a clock by 50, you create an enable signal that is high for 1 clock cycle in 50: process(clk) begin if rising_edge(clk) then if en = '1' then --only high once every 50 clocks --logic with 1/50 clock end if; end if; end process; Another question - have you created a testbench to test this code in the simulator before you go to the hardware (it will make your life easier)

I forgot to mention I will need to change the duty of the output. I'm new to modelsim, May I know how do I create the correct test bench?

cant find the problem with my code | Altera Community

16 Replies

Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
It doesnt output a clock. It uses an enable to only enable the logic inside the process once every N clocks (depending on how often you set the enable high). It does the same job as a 1/50 clock, but much more safely.
--- Quote End ---

Oh. May I know How do I control this enable? Am I suppose to carry out some sort of configuration? Or do I have to code it out again??

Altera_Forum

Honored Contributor

12 years ago

you generate it, like you would any enable:


signal cnt : unsigned(7 downto 0);
process(clk, reset)
begin
  if reset = '1' then
    cnt <= x"00";
    en <= '0';
  elsif rising_edge(clk) then
    
    --Create an enable that is high once every 256 clocks
    if cnt = 0 then  
      en <= '1';
    else
      en <= '0';
    end if;
  
    cnt <= cnt + 1;
  end if;
end process;

Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
A ripple clock is a clock that is generated via logic - ie. exactly what you have done - used a counter to create a slower clock from a faster one. It is better practice to use the same clock over the whole system and generate clock enables to only enable the target at the given rate. So to divide a clock by 50, you create an enable signal that is high for 1 clock cycle in 50:

process(clk) begin if rising_edge(clk) then if en = '1' then --only high once every 50 clocks --logic with 1/50 clock end if; end if; end process;

Another question - have you created a testbench to test this code in the simulator before you go to the hardware (it will make your life easier)
--- Quote End ---

Okay, so enable is also declared as a signal?

but how exactly do you "enable" the clock? Isn't it always running? I don't see any control signal to actually control the output do the clk? Clk is declared as an input port.
Altera_Forum
Honored Contributor
12 years ago
You dont enable the clock - you enable the logic. The clock is always running.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
You dont enable the clock - you enable the logic. The clock is always running.
--- Quote End ---

process(clk)
begin
if rising_edge(clk) then
if en = '1' then --only high once every 50 clocks
--logic with 1/50 clock
end if;
end if;
end process;

so when enable is '1' , am I suppose to output a '1'?? Cause the above code doesn't do anything in the if condition. If is it like that, how is it different from what I was doing? Isn't it still counting and outputting a pulsing signal.
Altera_Forum
Honored Contributor
12 years ago
The ripple clock discussion is not directly related to your question about LED0 output behaviour. It's a general point about bad design style. It's not being said that ripple clock style causes the behaviour.

Regarding LED0 output, you apparently never looked at the compilation warnngs. Otherwise you'll noticed that LED0 is reported as pin stucked to VCC. Why? LED0 isn't initialized in the design and never reset to 0. If you have enabled "power up don't care" in synthesis settings (by default), the respective register is optimized away in compilation. If you want LED0 set to '0' at start, include it in the reset action.

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cant find the problem with my code

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