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Altera_Forum
Honored Contributor
Honored Contributorcan't false path PLL input clock
I am getting a setup delay in my design, but the path includes the clock10 input transition time and all the time in the PLL. None of this should matter since everything is driven by the output cloc...
Altera_ForumHonored Contributor
Honored ContributorAre you doing this in TimeQuest?
The Data Arrival Path includes your clock delay + data path delay. The Data Required is the clock delay to the latch register. For slack calculations it will do Data_Arrival-Data_Required, which means the two clock delays will be subtracted from each other(and the result will not be 0, which means the clock delay is important and can't be fully ignored, although hopefully the skew is small)
