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YuukiSU's avatar
YuukiSU
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Can't execute the assertion debug on tutorial

Hello from Japan, I tried the assertion debug tutorial (page 197, Chapter 15 in Questa Tutorial PDF) with tutorial files. /<install_dir>/examples/tutorials/systemverilog/vlog_dut But, I ...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    We should remove/disable any testbench features that require advanced verification licenses.

    Coverage related code (which requires advanced verification licenses) can be disabled using vsim command option -nocvg.


    Best Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Simulating with vsim -nocvg disables covergroup object construction and removes the ability to run built-in covergroup methods during simulation. An svverification license is not required when -nocvg is used in the simulation.


Unfortunately, the Questa* - Intel® FPGA Edition simulator does not support SystemVerilog assertions as well.


Best Regards,

Richard Tan


  • YuukiSU's avatar
    YuukiSU
    Icon for New Contributor rankNew Contributor
    3 years ago

    I watched the debug demo video in the Questa-Intel FPGA Edition introduction page.
    In this video, the engineer introduces about "Assertion Debug" from 3:43.
    Questa*-Intel® FPGA Edition Debug Demo

    Also, it is mentioned about assertion support in the video about migration from Modelsim Intel FPGA Edition to Questa Intel FPGA Edition.
    I paste the snapshot of these videos.


    Are these introductions wrong?

    Best Regards,
    YuukiSU