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YuukiSU's avatar
YuukiSU
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Can't execute the assertion debug on tutorial

Hello from Japan, I tried the assertion debug tutorial (page 197, Chapter 15 in Questa Tutorial PDF) with tutorial files. /<install_dir>/examples/tutorials/systemverilog/vlog_dut But, I ...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    We should remove/disable any testbench features that require advanced verification licenses.

    Coverage related code (which requires advanced verification licenses) can be disabled using vsim command option -nocvg.


    Best Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

As it turns out, this is a limitation in Questa Intel FPGA Edition. It does not support simulating advanced verification features as mentioned in the error message (randomize, randcase, randsequence, covergroup).

You may need to use Questasim if you want to simulate advanced verification features.


Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.


YuukiSU's avatar
YuukiSU
Icon for New Contributor rankNew Contributor
3 years ago

I think "-nocvg" option disable these advanced verification features (rondomize, randcase, randsequence and covergroup), also I think the SystemVerilog Asertion feature w/o these advanced verification features is enable in Questa-Intel FPGA Edition. Are these right?

Best Regards,
YuukiSU