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Altera_Forum
Honored Contributor
Honored ContributorCan't determine definition of operator ""srl""
Hallo This is my first project with Altera. I am using the quatras 2 synthesis tool and simulink to generate a design for my FPGA. But when i try to synthesis the code i get the following error...
Altera_ForumHonored Contributor
Honored ContributorMove the cast external to the code that is converted to hdl. Do not have any floating point in any code that will be converted to hdl. Have all inputs as int 32 type.
