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Altera_Forum
Honored Contributor
10 years agoCan't determine definition of operator ""srl""
Hallo This is my first project with Altera. I am using the quatras 2 synthesis tool and simulink to generate a design for my FPGA. But when i try to synthesis the code i get the following error...
Altera_Forum
Honored Contributor
10 years agoYes i am using HDL coder from Simulink. I have MATALB 2014. The setup i have is a like the attached image. I make a subsytem out of the FIR interpolation filter and the CIC function. I am also attaching the CIC filter HDL code that i generate. I get the error at line 92 of the CIC filter file. If you need i can upload you the whole Simulink file and my function block.