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Altera_Forum's avatar
Altera_Forum
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16 years ago

Cannot Synthesize initialized RAM logic!!

Hello,

i wanted to initialize two two-dimensional arrays and used the following code segments:

parameter MEM_SIZE = 128; 
reg sigma_d2n;
reg Xn_k;
initial
begin
index=127;
for(k=0;k<MEM_SIZE;k=k+1)
begin
sigma_d2n=1;
Xn_k=15'b01;
end
end
now while doing analysis and synthesis, quartus (Quartus II 7.2 sp3) is showing the following error messege:

Error: Cannot synthesize initialized RAM logic "Xn_k"
Error: Cannot synthesize initialized RAM logic "Xn_k__dual"
Error: Can't elaborate inferred hierarchy "lpm_divide:Div0"
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 28 warnings
    Info: Allocated 255 megabytes of memory during processing
    Error: Processing ended: Tue Jun 09 17:12:38 2009
    Error: Elapsed time: 00:01:51
can anyone suggest any solution? Thanks in advance!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    The code compiles with recent Quartus version V9.0. But I guess, it's rather a problem related to the code part omitted from your post than a version issue. You also show an error message about a divider, that's not shown in the example.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    hi FvM,

    i've corrected my code for the divider...... but the other error messages were still there :( Then, i've turned off the 'auto RAM' option (i don't really know what I expected to happen) in the analysis and synthesis settings..... and it is showing the error messages no more!! can you explain what happened??
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I guess, the RAM has been synthesized as a file of registers rather than inferring internal RAM without the auto RAM option. Only suitable for very small RAM designs.

    I still expect, that the problem is in the remaining part of the code.