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Altera_Forum
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8 years ago

Cannot simulate TSE - Design unit not found

Hello, I am trying to simulate my module from sopc using the triple speed ethernet ip.when I try to simulate I get the error "altera_tse_mac.v(376): Instantiation of 'altera_tse_top_gen_host'...
Altera_Forum's avatar
Altera_Forum
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8 years ago

The tse Verilog file will be an encrypted IP core so it will look like gibberish when you open it. You will need a simulation model for it if there is one.