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Altera_Forum's avatar
Altera_Forum
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10 years ago

Cannot simulate ALTRCLKCTRL

Hello everyone,

I am trying to use ALTCLKCTRL IP in my design. The project compiles just fine, but when I try to simulate it using ModelSim (using NativeLink feature in Quartus II 16.0), I get the following errors:

# Loading altclkctrl_0.clk_gate_altclkctrl_0_sub# ** Error (suppressible): (vsim-10000) C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v(56): Unresolved defparam reference to 'sd1' in sd1.clock_type.# Time: 0 ps Iteration: 0 Instance: /tb_epcq_update/UUT/dclk_gate/altclkctrl_0/clk_gate_altclkctrl_0_sub_component File: C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v# ** Error (suppressible): (vsim-10000) C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v(57): Unresolved defparam reference to 'sd1' in sd1.ena_register_mode.# Time: 0 ps Iteration: 0 Instance: /tb_epcq_update/UUT/dclk_gate/altclkctrl_0/clk_gate_altclkctrl_0_sub_component File: C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v# ** Error (suppressible): (vsim-10000) C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v(58): Unresolved defparam reference to 'sd1' in sd1.lpm_type.# Time: 0 ps Iteration: 0 Instance: /tb_epcq_update/UUT/dclk_gate/altclkctrl_0/clk_gate_altclkctrl_0_sub_component File: C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v# Error loading design

Did anyone try using ALTCLKCTRL IP and had any success simulating the block. Any help is appreciated.

Thanks,

Yev

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi Yev,

    Did you resolve this problem? I'm having the same issue using Quartus Prime Lite Edition.

    Regards,

    Steve
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi Steve,

    Apparently, there is a bug that prevents Quartus to auto-generate a good working .v file for simulation. I did not have time chasing the problem, but instead abstracted out the block for simulation.

    Yev
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi Yev,

    Many thanks for your reply. I will not waste any more time trying to chase this issue but will do what you did and remove the module for simulation.

    Steve