Cannot Generate Timing Report in TimeQuest Timing Analyzer

Hi Ted,

When we debug your design with the JTAG interface, the JTAG signals TCK, TMS, TDI, and TDO are implemented as part of the design.

The altera_reserved_tck/tms/tdi pin is automatically generated for a design that uses a JTAG accessible module such as the Nios II debugger, SignalTap II logic analyzer, and In-System Memory Content Editor.

For timing constraint those pins

To constrain this JTAG clock, apply a 33-MHz clock constraint to this pin.

For the TimeQuest Timing Analyzer, use the following command:

create_clock -period "30.303 ns" -name {altera_reserved_tck} {altera_reserved_tck}

Reference

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd04282008_867.html

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand