i synthesis my design at synplify pro and then i fetched the VQM netlist and start fitting the design at Quartus. i got an error that there are two bits in a module at the design it can not be fit at the design i tried alot of fitting options but there is no solution FPGA is not fully utilized and i didn't see anything wired at the two bits that the tool said Thanks in advance

That Cyclone V (or Quartus) has so many problem to route signals ... I never seen such routing issue with any other FPGA's ...

Hi, Check out these two previous similar forum issues probably can help you. https://community.intel.com/t5/Programmable-Devices/While-running-the-cyclone-V-the-following-routing-problems-are/m-p/734484 https://community.intel.com/t5/Programmable-Devices/Fitter-can-t-fit-a-small-design-in-Cyclone-V-SE-that-fits-in-a/m-p/1315600 May check on the link below as well. https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/wvpr20k_vpr_no_route_suggestion_message.htm CAUSE: The Fitter was unable to route the design because it requires too many device routing resources. ACTION: There are multiple ways to diagnose or resolve a routing problem. Use one of the following methods to diagnose the routing problem: View the Global Routing Wire Utilization Map in GUI for overall routing congestion. View the Report Routing Utilization in Chip Planner for detailed routing congestion. Investigate signals identified by the router. Turn off timing optimization or alternatively just hold optimizations to see if timing constraints are the issue. Investigate non-global large fanout nets. Use one of the following methods to resolve the routing problem: Reduce routing demand by modifying the design. Reduce the interconnect complexity by localizing routing as much as possible. For example, transform a cross-bar interconnect into a ring-style interconnect to reduce interconnect complexity and improve routability (at the cost of increasing latency). If a global signal is unroutable, then delete global promotion of that signal. Add or remove Logic Lock regions. Reduce very aggressive timing constraints. Cut timing paths on cross-clock transfers. Change the Fitter Initial Placement Seed in the Advanced Fitter Settings dialog. Enable the Fitter Aggressive Routability Optimizations logic option in the Advanced Fitter Settings dialog. Reduce logic utilization. Select a larger device. Best Regards, Sheng p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

May I know any update? Do the suggestions help?

Still difficult to route using different actions like mentioned above but I can work with. Either the Cyclone V has limited routing capabilities, either Quartus has a bug.

Have you try with below compiler settings before: OPTIMIZATION_TECHNIQUE AREA (Balanced to Area) OPTIMIZATION_MODE "AGGRESSIVE AREA" SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 (3 to 2) ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS （Auto to Always） PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF （ON to OFF） Allow Register Duplication (Off) Remove Duplicate Registers (On) Auto Register Duplication (Off) Logic Cell Insertion - Logic Duplication (Off) Perform Register Duplication for Performance (Off) Fitter Aggressive Routability Optimizations (Always) Auto Packed Registers (Minimize Area with Chains) Optimize IOC Register Placement for Timing (Pack All IO Registers) Perform Logic to Memory Mapping for Fitting (On) Check also chip planner as well must be some place highly hotspot.

cannot fit the design in the device Cyclone V

16 Replies

ShengN_altera
Super Contributor
3 years ago
You could provide the fitter report personally to me via this email id qi.sheng.ng@intel.com
ShengN_altera
Super Contributor
3 years ago
After going through the fitter report, looks like still not that extremely compact yet should be not a problem for routing.
Btw, glad to know that you have successfully route the design after a retry.

Thank you,
Sheng
AEsqu
Contributor
3 years ago
In the logic lock region in blue , when it fails to route the Cortex M33, there are high wire utilization.
ShengN_altera
Super Contributor
3 years ago
The Compiler's messages contain information about average and peak interconnect usage. Peak interconnect usage over 75%, or average interconnect usage over 60%, can indicate difficulties fitting your design. Similarly, peak interconnect usage over 90%, or average interconnect usage over 75%, show increased chances of not getting a valid fit.

Based on the picture, I think your design should be no problem at routing for the time being.
Do let me know if you need any further help on this.

Thank you,
Sheng

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cannot fit the design in the device Cyclone V

16 Replies

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