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This may be a bug caused by an incorrect replacement of the Altera name by Intel in the ip library.
Until this is fixed, I could fix this like this:
> locate the .lst file of the missing IP in your IntelFGPA program directory, for example for the missing PLL, locate: "pll_wizard.lst"
> Change the text:
"<ALIAS>Altera PLL v18.0</ALIAS> "
(and higher version numbers) to:
"<ALIAS>PLL Intel FPGA IP v18.0</ALIAS>"
I hope this helps you also for the other IPs.
Due to all documentation update notices due to the Altera -> Intel re-branding, it is hard to see the real improvements that are being made...
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That seems to work. It looks like the ALIAS in the .lst file must be edited to match the generated core. In my case, I have a file MAIN_PLL.vhd that I opened in Pre 18.0 in order to start the wizard. At the top it has:
-- megafunction wizard: %PLL Intel FPGA IP v18.0%
which matches what you said to change the ALIAS to.
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