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Altera_Forum
Honored Contributor
Honored ContributorCannot edit the generated PLL Intel FPGA IP v18.0
Hi All, I am using Quartus Prime v18.0 and generated PLL IP v18.0. I have successfully generated the PLL and added into the project but when I tried to modify it in the IP components, the Me...
Altera_ForumHonored Contributor
Honored ContributorI have the same problem. My current project was upgraded from 16.1. But, I don't think the upgrade matters. I created a new PLL. Creation seems to be okay. But, afterwards you can not edit the PLL. This is a Cyclone V GX. Running on Windows 8.1.
Painful time consuming workaround is to open the top ".v" file of the PLL. Save the "Retrieval info:" from that file. Remove the old generated IP. Generate new IP from the IP Catalog while manually reading the "Retrieval Info:" to determine GUI settings. In other words, I have not found a way to edit PLL Intel FPGA IP after it is generated. (I wonder if this is due to renaming stuff from Altera to Intel.) Hope there is a fix soon.
