I started my HDL carrier with ABEL 15 years back. Those days even counters were laid down manually with flip-flops. We changed loyalty to Altera and hence a shift from ABEL to AHDL.
ADHL was adorable. There was no big conceptual difference from ABEL, but reusing counters, comparators was saving lots of work and as chip densities grew our code sizes grew too and we had no difficulty growing up.
For the last project we were advised that Altera was depreciating AHDL and we needed to shift to perphaps Verilog. It was a sad movement.
Learning Verilog was not entirely easy. The syntax was confusing. For an "gates guy" thinking in terms of flip-flops and gates, the "high level" of Verilog was pretty unnatural and difficult.
Thank goodness, we did not do anything drastic like running a Xilinx convertor on AHDL, or strating from scratch using verilog.
We decided to do only new modules in Verilog.
But as project progressed we decided that modules with complex alogs be in AHDL and we have some wrapper.
And lol at the end there were only two places we used Verilog. 1. To create an interface from SoPC to our logic 2. Test bench for simulation in Modelsim. Recently even (1) was removed when Qsys entered! Had there been a vector waveform input option for Modelsim net writer even (2) would have been avoided! But had the wonderful native simulator been supported would it not been marvellous.
We use the latest Quartus edition, the latest FPGA, the latest Nios suite and the unrelenting language AHDL.
The support that Altera continues to provide for AHDL is the reason for all feat which we are proud of and I pray Altera continues to keep this wonderful language glorious.
Ravi
Honored Contributor
