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ARach7's avatar
ARach7
Icon for New Contributor rankNew Contributor
6 years ago

Can you explain why the 3 "arriav" libraries are not listed in library mapping file for VCS, the synopsys_sim.setup that is generated under /simulation/scsim ?

Test-case:​ $QUARTUS_ROOTDIR/qdesigns/binary_cam. At EDA simulation library compiler, choose CycloneV and arriav and compile the in Verilog. At the synopsys_sim.setup file created for the ex...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi, Can you help me to understand more on the problem statement ? 1) Which Quartus version that you are using ? 2) Which VCS MX version that you are using ? 3) And this sim error issue is impacting which Intel FPGA IP ? Arria V fpll IP ? 4) How can I duplicate this sim error issue ? Is there some example design that I can use or you will be able to share your sim design project here ? Thanks. Regards, dlim
  • ARach7's avatar
    ARach7
    Icon for New Contributor rankNew Contributor
    6 years ago
    Using Quartus 18.1 Using VCS 2017.12. It’s a general question: what will trigger Quartus scripts to add arriav* logical libraries (arriav_hssi_ver, arriav_ver, arriav_pcie_hip_ver) into synopsys_sim.setup? Suppose my testbench file (that is added to project file using “compile testbench”) has an instance of “altera_arriav_pll”. That “altera_arriav_pll” cell will needs staff from arriav, but these libraries are not found in synopsys_sim.setup, although they were compiled with EDA simulation library compiler. thanks