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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Can the setup/hold time violated be removed with TimeQuest?

I am a beginner in STA using TimeQuest. Now I have a basic understanding about STA using TimeQuest. I have a question which confused me: Take an example, if in a design, there is a path, from n...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Thanks. Yes, fiddling with the Quartus synthesis/fitting options may work in some cases, but the options are very limited.

You mentioned "manually placing some cells", do you mean put a register in a failed path to increase a step pipeline as I described?

Thanks.

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Unfortunately the person answering this is completely wrong.

Timequest set_output_delay and set_input_delay constraints are used to set the external PCB and device input and output delay (including setup and hold time).

Timequest does a very good job of this. There is no need to be fiddling with manually placing cells. Search for TimeQuest User Guide by Ryan Scoville.