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Well through .sdc file you can guide the timequest to do correct constraining.
Constraints like target clock frequency,false paths,multicycle paths etc if there are to be set.
Now supposetake an example there is a path between asynchronous clock domain then its is bound to fail timing and in that case a false path needs to be set.
Now coming to what you mentioned that point a and b are in the same clock domain with time period 10ns then provided other constraints are proper (you have taken care of false paths or multicycle paths if any) in the design then i think you need to review your RTL.
If you are failing by some 10 Mhz then you can try some optimization switches through .qsf file. I have seen these optimization switches improving the design performance by 20 MHz also.
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Thanks very much, so generally speaking, my understanding is right. I don't know what is .qsf file and I have never used it. I should investigate what it is and how to use it.
The most common approach in my case seems to be: the path from "a" to "b" failed, then we can try to break this path through add a register between then to add a pipeline.
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